Publications



       
       
       


Conference Papers
  1. N. Koo, S.H. Cho, "A 27.8μW Biopotential Amplifier Tolerant to 30VPP Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS," IEEE Int’l Solid-State Circuits Conference (ISSCC), 2019.    
                
  2. S. Park, G.H.Lee, S.H.Cho, "A 2.69µW Dual Quantization‐based Capacitance‐to‐Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18µm CMOS," IEEE Symposium on VLSI Circuits, 2018.                                                   
  3. D. Jang, S. H. Cho, "A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop," IEEE Int’l Solid-State Circuits Conference (ISSCC), 2018.

  4. D. Kim, S. H. Cho, "A Supply Noise Insensitive PLL with a Rail-to-Rail Swing Ring Oscillator and a Wideband Noise Suppression Loop," IEEE Symposium on VLSI Circuits, 2017.

  5. M. Kim, S. H. Cho, "A 0.8V, 37nW, 42ppm/°C, Sub-Bandgap Voltage Reference with PSRR of -81dB and Line Sensitivity of 51ppm/V in 0.18um CMOS," IEEE Symposium on VLSI Circuits, 2017. 
     
  6. J. Lee, H. Kim, S.H. Cho, "A 255nW Ultra-High Input Impedance Analog Front-End for Non-contact ECG Monitoring," IEEE Custom Integrated Circuits Conference (CICC), 2017.
         
  7. H. Kim, Y. Kim, T. Kim, H. Park, S. Cho, A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2016.
          
  8. J.S. Choi, G. Kim, H.H. Yang, J.B. Yoon, and S.H. Cho, "A Surface Conductance based Fully Integrated Standard CMOS Humidity Sensor without Post-Processing," IEEE Sensors Conference, 2015.

  9. J. Lee, and S.H. Cho, "A Motion-tolerant Heart Rate Detection Method Using Bio-impedance and MUSIC Algorithm," IEEE Sensors Conference, 2015.

  10. J. Lee, S.H. Yeon, and S.H. Cho, "All Electrical and Real-time ECG, Respiration, Airflow, and Skin Conductance Monitoring System," Int’l SoC Conference (ISOCC), 2015.

  11. J. Lee, and S.H. Cho, "A Heart Rate Detection Method Using Bio-Impedance and MUSIC Algorithm with Reduced Sensitivity to Motion," the IEEE Engineering in Medicine and Biology Society (EMBC), 2015.

  12. H. Kim, J. Sang, H. Kim, Y. Jo, T. Kim, H. Park, S.H. Cho, “A 5GHz -95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2015.

  13. J. Lee, P. Park, S. Cho, M. Je, “A 4.7MHz 53μW Fully Differential CMOS Reference Clock Oscillator with –22dB Worst-Case PSNR for Miniaturized SoCs,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2015.
         
  14. W. Yu, K.S. Kim, and S.H. Cho, "A 148fsrms Integrated Noise 4MHz Bandwidth All-Digital Second-Order ΔΣ Time-to-Digital Converter Using Gated Switched-Ring Oscillator," IEEE Custom Integrated Circuits Conference (CICC), 2013.                                                                                                                
  15. K.S. Kim, W. Yu, and S.H. Cho, "A 9b, 1.12ps Resolution 2.5b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register ," IEEE Symposium on VLSI Circuits, 2013.                                                                                                           
  16. W. Lee, and S.H. Cho, "An Integrated Pulse Wave Velocity Sensor using Bio-impedance and Noise-shaped Body Channel Communication," IEEE Symposium on VLSI Circuits, 2013.                                                                                                              
  17. K.S. Kim, Y.H. Kim, W. Yu and S.H. Cho, "A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier," IEEE Symposium on VLSI Circuits, 2012.

  18. D.Park and S.H. Cho“A 14.2mW 2.55-to-3GHz Cascaded PLL With Reference Injection, 800MHz Delta-Sigma Modulator and 255fsrms Integrated Jitter in 0.13μm CMOS ,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2012.

  19. P.Park, J. Park, H. Park and S.H. Cho, “An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS”, IEEE Int’l Solid-State Circuits Conference (ISSCC), 2012.

  20. J. Kim, W. Yu, H.-K. Yu, and S.H. Cho, “A digital intensive receiver front-end using VCO-based ADC with an embedded 2nd-order anti-alias Sinc filter in 90nm CMOS,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2011. 

  21. J. Lee and S.H. Cho, “A 210nW 29.3 ppm/degree 0.7 V Voltage Reference with a Temperature Range of -50 to 130 degree in 0.13um CMOS,” IEEE Symposium on VLSI Circuits, 2011. 

  22. P. Park, D. Park, S.H. Cho, ”A Fractional-N Frequency Synthesizer using High-OSR Delta-Sigma Modulator and Nested-PLL,” IEEE Custom Integrated Circuits Conference (CICC), 2011. 

  23. Y. H. Kim, S. H. Cho, ”A Time-Domain Flash ADC Immune to Voltage Controlled Delay Line Non-Linearity (invited),”, IEEE ASICON, 2011. 

  24. D. Park and S.H. Cho, ”Design Techniques for Ultra Low-Power Phase-Locked Loops (invited)”, IEEE MWSCAS, 2011. 

  25. J. Kim, J. Lee, and S.H. Cho, ”Digital-Intensive Analog Circuits for Highly-Digitized RF Receivers (invited),” IEEE MWSCAS, 2011. 

  26. Y.-G. Yoon, S.H. Park, S.H. Cho, ”A Time-Based Noise Shaping Analog-to-Digital Converter using a Gated-Ring Oscillator,” IEEE MTT-S International Workshop Series, 2011. 

  27. H. Choi and S.H. Cho, “Time-interleaved Single-slope ADC using Counter-based Time-to-Digital Converter” IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2011.

  28. J. Lee, J. Kim and S.H. Cho“A 1.8 to 2.4-GHz 20mW Digital-Intensive RF Sampling Receiver with a Noise-Canceling Bandpass Low-Noise Amplifier in 90nm CMOS,” IEEE RFIC Symposium, 2010. 

  29. W. Lee and S.H. Cho, “A 2.4-GHz Reference Doubled Fractional-N PLL with Dual Phase Detector in 0.13-um CMOS,” IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2010. 

  30. S.-P. Lee and S.H. Cho“A Background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop,” IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2010. 

  31. Y.-H. Kim, J. Lee and S.H. Cho “A 10-bit 300MSample/s Pipelined ADC using Time-Interleaved SAR ADC for Front-End Stages,” IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2010. (Acceptance Rate: 45%) 

  32. Y.-G. Yoon and S.H. Cho, “A 1.5-GHz 63dB SNR 20mW Direct RF Sampling Bandpass VCO-based ADC in 65nm CMOS,” IEEE Symposium on VLSI Circuits, 2009. (Acceptance Rate: 35%) 

  33. J. Lee and S.H. Cho, “An 80uW, 10MHz, 67 ppm/degree CMOS Reference Clock Oscillator with a Temperature Compensated Loop in 0.18um CMOS,” IEEE Symposium on VLSI Circuits, 2009. 

  34. S.H. Jeon, Y. Nam and S.H. Cho “A Neural Recording and Stimulation Technique Using Passivated Electrodes and Micro-Inductors,” IEEE A-SSCC, 2009. 

  35. M.C. Cho, J.Y. Kim, S.H. Cho, “A Bio-Impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity Using Small Body Area,” IEEE International Symposium on Circuit and System (ISCAS), 2009. 

  36. S. Bang, C. Lee, J.Park, M.C Cho, Y.-G. Yoon and S.H. Cho “A Pulse Transit Time Measurement Method Based on Electrocardiography and Bioimpedance,” IEEE Int’l Conference on Biomedical Circuits and Systems (BioCAS), 2009. 

  37. M.C. Cho, Y.-G. Yoon and S.H. Cho,”Design of Highly Programmable Bio-Impedance Measurement IC in 0.18um CMOS,” Int’l SoC Conference (ISOCC), 2009. 

  38. S.S. Woo, J.-H. Lee and S.H. Cho, “A Ring Oscillator-based Temperature Sensor for U-Healthcare in 0.13um CMOS,” Int’l SoC Conference (ISOCC), 2009. 

  39. Y.-H. Kim and S.H. Cho, “A Time-based Successive Approximation Register Analog-to-Digital Converter using a Pulse Width Modulation Technique with a Single Capacitor,” Int’l SoC Conference (ISOCC), 2009. 

  40. Y.-G. Yoon and S.H. Cho, “A Linearization Technique for Voltage-Controlled Oscillator-based ADC,” Int’l SoC Conference (ISOCC), 2009. 

  41. W. Lee and S.H. Cho “A 900MHz 2.2mW Spread Spectrum Clock Generator based on Direct Frequency Synthesis and Harmonic Injection Locking,” Int’l SoC Conference (ISOCC), 2009. 

  42. S.J. Kim and S.H. Cho, “A Variation Tolerant Reconfigurable Time Difference Amplifier,” Int’l SoC Conference (ISOCC), 2009. 

  43. S.H. Park, C.W. Min, S.H. Cho“A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13um CMOS,” IEEE International Symposium on Circuit and System (ISCAS), 2009. 

  44. S.J. Kim, M. C. Cho, J. Park, K. Song, Y. Kim, S.H. Cho, “An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder,” IEEE International Symposium on Circuit and System (ISCAS) , pp. 660 -663, 2008. (Acceptance Rate: 48%) 

  45. D. Park, W. Lee, S. Jeon and S.H. Cho“A 2.5-GHz 860uW Charge-Recycling Fractional-N Frequency Synthesizer in 130nm CMOS,” IEEE Symposium on VLSI Circuits, 2008. (Acceptance Rate: 20%) 

  46. J. Lee, K. Kim, J. Lee, T. Jang and S.H. Cho, “A 480-MHz to 1-GHz Sub-picosecond Clock Generator with a Fast and Accurate Automatic Frequency Calibration in 0.13um CMOS,” Proceedings of IEEE A-SSCC, 2007. (Acceptance Rate: 32%) 

  47. J. Lee and S.H. Cho, “A 470-µW Multi-Modulus Injection-Locked Frequency Divider with Division Ratio of 2, 3, 4, 5 and 6 in 0.13um CMOS,” Proceedings of IEEE A-SSCC, 2007.(Acceptance Rate: 32%) 

  48. J. Lee and S.H. Cho“A Low Power Transmitter for Phase-Shift Keying Modulation Schemes,” IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006. (Acceptance Rate:59%) 

  49. H. Chung, E. Hong, K. Kim, S.H. Cho“Optimum Supply Voltage and Sleep Transistor Sizing for Energy Minimization in Latency-Constrained MTCMOS Circuits,” International SoC Design Conference(ISOCC), pp. 365 -368, 2006. (Acceptance Rate: N.A.) 

  50. S.H. Cho and K.E. Kim “Variable Bandwidth Allocation Scheme for Energy Efficient Wireless Sensor Network”, IEEE International Conference on Communications (ICC), 2005. (Acceptance Rate: 32%)

  51. D. Park and S.H. Cho, “An Adaptive Body-Biased VCO with Voltage-Boosted Switched Tuning in 0.5-V Supply,” European Solid-State Circuits Conference (ESSCIRC), pp. 444 -447, 2006. Acceptance Rate: 36%) 

  52. D. Park and S.H. Cho, “A Power-Optimized CMOS LC VCO with Wide Tuning Range in 0.5-V Supply,” IEEE International Conference on Circuits and Systems (ISCAS), 2006. (Acceptance Rate: 59%) 

  53. J.Kim and S.H. Cho“A Time-Based Analog-to-Digital Converter Using a Multi-Phase Voltage-Controlled Oscillator,” IEEE International Conference on Circuits and Systems (ISCAS), 2006. (Acceptance Rate: 59%) 

  54. S.H. Cho, S.M. Ock, S.H. Lee, and J.S. Lee “A Low Power Pipelined Analog-to-Digital Converter using Series Sampling Capacitors”, IEEE International Conference on Circuits and Systems (ISCAS), 2005. (Acceptance Rate: 69%) 

  55. K. Gulati, C. Munoz, S.H. Cho, G. Manganaro, M. Lugin, M. Peng, A. Pulincherry, J. Li, A. Bugeja, A. Chandrakasan and D. Shoemaker, “A Highly Integrated Analog Baseband Transceiver Featuring a 12-bit 180MSPS Pipelined A/D Converter for Multi-Channel Wireless LAN” , IEEE Symposium on VLSI Circuits, 2004. (Acceptance Rate: 32%) 

  56. S.H. Cho, A. Chandrakasan, “A 6.5GHz CMOS FSK modulator for wireless sensor applications”, IEEE Symposium on VLSI Circuits, pp.182–185, 2002. (Acceptance Rate: 38%) 

  57. A. Chandrakasan, R. Min, M. Bhardwaj, S.H. Cho, and A. Wang ”Power Aware Wireless Microsensor Systems”, Proceedings of ESSCIRC, pp.47–54, September 2002. (Keynote paper, Invited) 

  58. A. Wang, S.H. Cho, C. Sodini and A. Chandrakasan, “Energy Efficient Modulation and MAC for Asymmetric RF Microsensor systems,” Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, pp.106–111, 2001. (Acceptance Rate: 24%) 

  59. E. Shih, S.H. Cho, N. Ickes, R. Min, A. Sinha, A. Wang, and A. Chandrakasan, ”Physical Layer Driven Algorithm and Protocol Design for Energy-Efficient Wireless Sensor Networks”, Proceed¬ings of ACM/IEEE International Conference on Mobile Computing and Networking (MOBICOM), pp.272–287, 2001. (Acceptance Rate: 11%) 

  60. S.H. Cho, A. Chandrakasan, “Energy Efficient Protocols for Low Duty Cycle Wireless Microsensor Networks”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) , pp.2041–2044, 2001. (Acceptance Rate: 51%) 

  61. E. Shih, S.H. Cho, B. Calhoun, A. Chandrakasan, “Energy Efficient Link Layer for Wireless Microsensor Networks,” Proceedings of IEEE Workshop on VLSI, pp.16–21, 2001. 

  62. R. Min, M. Bhardwaj, S.H. Cho, E. Shih, A. Sinha, A. Wang and A. Chandrakasan “ Low-Power Wireless Sensor Networks,” IEEE Fourteenth International Conference on VLSI Design, pp.205–210, 2001. 

  63. R. Min, M. Bhardwaj, S.H. Cho, A. Sinha, E. Shih, A. Wang and A. Chandrakasan “ An Architecture for a Power-Aware Distributed Microsensor Node,” IEEE Workshop on Signal Processing Systems (SiPS ’00), pp.581–590, 2000.

  64. A. Chandrakasan, R. Amirtharajah, S.H. Cho, J. Goodman, G. Konduri, J. Kulik, W. Rabiner, A. Wang “Design Considerations for Distributed Microsensor Systems,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp.279–286, 1999. 

  65. S.H. Cho, T. Xanthopoulos and A. Chandrakasan, “An Ultra Low Power Variable Length Decoder Exploiting Codeword Distribution,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 177–180, 1998. 

  66. S.H. Cho, T. Xanthopoulos and A. Chandrakasan“Design of Low Power Variable Length Decoder Using Fine Grain Non-Uniform Table Partitioning,” IEEE International Symposium on Circuits and Systems, pp. 2156–2159, 1997.