NEWS‎ > ‎

Kwangsuk's paper published in JSSC.

posted Apr 9, 2014, 11:19 PM by CCSLab Kaist
K.S. Kim, Yu, W and S.H. Cho, " A 9b, 1.12ps resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register," IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1007 - 1016, 2014. 
Comments