K.S. Kim, Y.H. Kim, W. Yu and S.H. Cho, "A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier," IEEE Journal of Solid-State Circuits, vol. 48, no.4, pp.1009-1017, 2013.

 W. Yu, J. Kim, K.S. Kim, S.H. Cho, "A Time-Domain High-Order MASH Delta-Sigma ADC using Voltage-Controlled Gated-Ring Oscillator," IEEE Transactions on Circuits and Systems –I, vol. 60, no.4, pp.856-866, 2013.