Publication

Journal Papers 

1. H. Choi, and S.H. Cho, “A 7.5GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120x Multiplying Factor and 92.3fs RMS Jitter Including Reference Spur”, IEEE Journal of Solid-State Circuits, Accepted. (PIM)

2. P. Park, J. Lee and S.H. Cho, “A PVT-Insensitive Sub-ranging Current Reference Achieving 11.4-ppm/°C from −20 °C to 125 °C”, IEEE  Journal of Solid-State Circuits, Accepted. (PIM)

3. J. Oh, and S.H. Cho, “A 0.001-mm2, 1.15-11 GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND-based Phase Detector in 28-nm CMOS”, IEEE Solid-State Circuits Letters, vol. 7, pp. 247-250, 2024. (PIM)

4. Y. Kim, T. Jang, S.H. Cho, "A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor" IEEE J. Solid-State Circuits, Early Access. (글로벌 공동연구&IITP글로벌)

5. J. Seo, M. Seok, S.H. Cho, "A 44.2-TOPS/W CNN Process With Variation-Tolerant Analog Datapath and Variation Compensating Circuit", IEEE J. Solid-State Circuits, vol. 59, no. 5, 2024. (PIM & 글로벌 공동연구)

6. P. Park, W. Lee, S.H. Cho, "An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-wavelength PPG for Accurate HR Estimation" IEEE Trans. on Biomedical Circuits and Systems, vol. 17, no. 5, 2023.(IITP RADAR & 포공 바이오센터)

7. M. Kim, S.H. Cho, "An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier" IEEE Transactions on Circuits and Systems - I, vol. 70, no. 2, 2023. (이어달리기 & PIM)

8. S. Park, H. Chae, S.H. Cho, "A 3.68aFrms Resolution Continuous-Time Bandpass ΔΣ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18μm CMOS", IEEE J. Solid-State Circuits, vol. 58, no. 6, 2023. (중견연구, IITP RADAR)

9.  Y. Jung, S. Lee, H. Kim, S.H. Cho, "A Supply Noise Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM" IEEE J. Solid-State Circuits, vol. 58, no. 1, 2023. (이어달리기 & PIM)

10. N. Koo, H. Kim, S.H. Cho, "43.3µW Biopotential Amplifier with Tolerance to Common-Mode Interference of 18Vpp and T-CMRR of 105dB in 180nm CMOS" IEEE J. Solid-State Circuits, vol. 58, no. 2, 2023. (이어달리기 & 중견연구)

11. S. Park, J-H. Seol, L. Xu, S.H. Cho, D. Sylvester, and D. Blaauw, "A 43 nW, 32 kHz, A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance", IEEE J. Solid-State Circuits, vol. 57, no. 4, 2022. (중견연구)

12. D. Kim, and S.H. Cho, “Adaptive Clocking Using Supply Tracking Clock Modulator With Background-Calibrated Supply Sensitivity”,  IEEE Solid-State Circuits Letters, vol. 5, 2022. (중견연구, IITP RADAR)

13. M. Kim, and S.H. Cho, “A Single BJT Bandgap Reference with Frequency Compensation Exploiting Mirror Pole”,  IEEE J. Solid-State Circuits, vol. 56, no. 10, 2021. (중견연구, IITP 이어달리기) 

14. N. Koo and S.H. Cho, "A 24.8µW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180nm CMOS," IEEE J. Solid-State Circuits, vol. 56, no. 2, 2021. (중견연구, IITP 이어달리기) 

15. M. Kim, and S.H. Cho, “A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18-µm CMOS”, IEEE Solid State Circuits Letters, vol. 3, 2020. (중견연구, IITP 이어달리기)

16. D. Kim, E. Lee, J. Kim, P. Park, S.H. Cho, “A sleep apnea monitoring IC for respiration, heart-rate, SpO2 and pulse-transit time measurement using thermistor, PPG and bodychannel communication”, IEEE Sensors Journal, vol. 20, no. 4, 2020. (ERC,탈평면)

17. S. Park, G-H. Lee, and S.H. Cho, "A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 54, no. 10, 2019. (중견연구)

18. D.-K. Jung, J.-O. Seo, and S.H. Cho, "An On-Chip Thermal Monitoring System with a Temperature Sensing Area of 52 µm2 in 180nm CMOS," IEEE Trans. on Circuits and Systems - II: Express Briefs, vol. 66, no. 10, 2019. (ERC 탈평면)

19. D. Kim, K. Kim, W. Yu, S.H. Cho, "A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits," IEEE Trans. on Circuits and Systems - II: Express Briefs, vol. 66, no. 10, 2019.

20. D. Kim and S.H. Cho, "A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise," IEEE Trans. on Circuits and Systems - II: Express Briefs, vol. 66, no. 2, 2019. (ERC 탈평면)

21. J. Lee, D.H. Jang, S. Park, and S.H. Cho, "A Low-power Photoplethysmogram-based Heart Rate Sensor using Heart Beat Locked Loop," IEEE Trans. on Biomed. Circuits and systems, vol. 12, no. 6, 2018. (ERC 중견연구) 

22. Y. Jo, H.J. Kim, and S.H. Cho, "A 3.2GHz Supply Noise Insensitive PLL using a Gate Voltage boosted Source-Follower Regulator and Residual Noise Cancellation," IEEE Trans. on VLSI Systems, vol. 26, no.10, 2018. (ERC)

23. J. Lee, G-H. Lee, H. Kim, and S.H. Cho, "An Ultra-high Input Impedance Analog Front-end with Self-calibrated Positive Feedback," IEEE J. Solid-State Circuits, vol. 53, no. 8, 2018. (ERC 탈평면)

24. H. I. Kim, Y.J. Kim, T.I. Kim, H.J. Ko, and S.H. Cho, "A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique," IEEE J. Solid-State Circuits, vol. 52, no.11, 2017. (ERC)

25. J.H. Kang, S. Park, and S.H. Cho, " A Relative Permittivity-Based Air Pressure Sensor Using Standard CMOS Process," IEEE Sensors Journal, vol. 17, no. 12, 2017. (ERC)

26. Y.J. Kim, K. Song, D. Kim, and S.H. Cho, "A 2.3mW, 0.01mm2, 1.25GHz Quadrature Signal Corrector with 1.1ps error for Mobile DRAM Interface in 65nm CMOS," IEEE Trans. on Circuits and Systems - II: Express Briefs, vol. 64, no. 4, 2017. (ERC)

27. Y.H. Kim and S.H. Cho, "A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source," IEEE Transactions on VLSI Systems, vol. 24, no. 7, pp. 2570-2579, 2016. (도약 과제)

28. W. Yu, K.S. Kim, and S.H. Cho, “A 0.22 psrms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter,” IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1251 - 1262, 2015.

29. J. Kim, Y-H. Kim, K.S. Kim, W. Yu, S.H. Cho, "A Hybrid-domain Two-step Time-to-Digital converter Using Switch-Based Time-to-Voltage converter and SAR ADC," IEEE Trans. on Circuits and Systems - II, vol. 62, no. 7, pp.  631 - 635, 2015.

30. W. Lee and S.H. Cho, “Integrated All Electrical Pulse Wave Velocity & Respiration Sensors using Bio-impedance,” IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 776 - 785, 2015.                                                                                                                                                     

31. W. Yu, K.S. Kim, and S.H. Cho, "A 148fsrms Integrated Noise 4MHz Bandwidth Second-Order Delta-Sigma  Time-to-Digital Converter With Gated Switched-Ring Oscillator," IEEE Transactions on Circuits and Systems - I, vol. 61, no. 8, pp. 2281 - 2289, 2014.

32. K.S. Kim, Yu, W, and S.H. Cho, " A 9b, 1.12ps resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register," IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1007 - 1016, 2014.                                          

33. K.S. Kim, Y.H. Kim, W. Yu, and S.H. Cho, "A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier," IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 1009-1017, 2013. 

34. W. Yu, J. Kim, K.S. Kim, S.H. Cho, "A Time-Domain High-Order MASH Delta-Sigma ADC using Voltage-Controlled Gated-Ring Oscillator," IEEE Transactions on Circuits and Systems –I, vol. 60, no. 4, pp. 856-866, 2013.                                              

35. D. Park, S.H. Cho, "A 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800MHz ΔΣ modulator in 0.13μm CMOS," IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2989-2998, 2012.                                                          

36. J. Kim, W. Yu, S.H. Cho, "A Digital-Intensive MMMB Receiver Using a Sinc2 filter-Embedded VCO-Based ADC," IEEE Transactions on Microwave Theory and Techniques,  vol. 60, no.10, pp.3254-3262, 2012.

37. P.W. Park, D. Park, S.H. Cho, “A 2.4GHz Fractional-N Frequency Synthesizer with High-OSR DS Modulator and Nested PLL,” IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2433-2444, 2012.

38. J. Lee, S.H. Cho, "A 1.4 µW 24.9 ppm/◦C current reference with process insensitive temperature compensation in 0.18 µm CMOS," IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2527-2534, 2012.

39. J. Lee, W. Lee, S. Cho, "A high-frequency compensated crosstalk and ISI equalizer for multi-channel on-chip interconnect in 130-nm CMOS," IEEE Journal of Emerging and Selected Topics in Cir. & Sys., vol.2, no.2, pp. 314-321, 2012.

40. T. Jang, J. Kim, Y.G. Yoon, S.H. Cho, ” A Highly-Digital VCO-based Analog-to-Digital Converter using Phase Interpolator and Digital Calibration,” IEEE Transactions on VLSI Systems, vol. 20, no. 8, pp. 1368-1372, 2012. 

41. J. Lee, W. Lee, S. H. Cho, “A 2.5-Gb/s on-chip interconnect transceiver with crosstalk and ISI equalizer in 130 nm CMOS,” IEEE Transactions on Circuits & Systems-I, vol. 59, no. 1, pp. 124-136, 2012.

42. J. Lee, S. Park and S.H. Cho, “A 470-uW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider with an In-Phase Dual-Input Injection Scheme,” IEEE Transactions on VLSI Systems, Vol. 19, No. 1, pp. 61-70, 2011. 

43. P.W. Park, D. Park and S.H. Cho, “A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13um CMOS”, IEEE Microwave and Wireless Components Letters, Vol. 20 No.1 pp.52-54, 2010. 

44. J. Kim, T.-K. Jang, Y.-G. Yoon and S.H. Cho, “Analysis and Design of Voltage-Controlled Oscillator-Based Analog-to-Digital Converter,” IEEE Transactions on Circuits and Systems - I, Vol. 57, No. 1, pp.18-30, 2010. 

45. K.S. Kim, J. Kim, S.H. Cho, ”Nth-order multi-bit delta-sigma ADC using SAR quantiser,” Electronics Letters, 2010. 

46. S.-J. Kim, M.C. Cho, and S.H. Cho, ”An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder,” IEICE Transactions on Electronics, Vol.E93-C, No.6, pp.785-795, 2010. 

47. D. Park and S.H. Cho “Design Techniques for a Low-Voltage VCO with Wide Tuning Range and Low Sensitivity to PVT Variations,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 4, pp.767-774, 2009. 

48. D. Park and S.H. Cho “A 1.8 V 900-µW 4.5 GHz VCO and Prescaler in 0.18µm CMOS Using Charge-Recycling Technique,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 2, 2009. 

49. J. Lee, S. Kim, S. Jeon, W. Lee, and S.H. Cho, “A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13 um CMOS,” IEICE Transactions on Electronics, Vol. E92-C, No. 4, pp. 589-591, 2009. 

50. Y.-G. Yoon, J. Kim, T. Jang, and S.H. Cho, “A Time-based Bandpass ADC using Time-Interleaved Voltage-Controlled Oscillators”, IEEE Transactions on Circuits and Systems -I, Vol. 55, No. 11, pp. 3571-3581, 2008. 2009 IEEE Transactions on Circuits and Systems Guillemon-Cauer Best Paper Award 

51. S.H. Cho “A Self Noise Canceling Technique for Voltage-Controlled Oscillators,” Electronics Letters, Vol. 44, No. 25, pp. 1436-1437, 2008. 

52. J.H. Han and S.H. Cho “Digitally Controlled Oscillator with High Frequency Resolution using Novel Varactor Bank,” Electronics Letters, Vol. 44, No. 25, pp. 1450-1452, 2008. 

53. Y. Ku and S.H. Cho, “An Optimum Current Mirror Ratio for Low Phase Noise LC-VCO,” IEEE Microwave and Wireless Components Letters, Vol. 18, No. 12, pp. 809–811, 2008. 

54. J. Lee and S.H. Cho, “A Quadrature Modulation Transmitter Using Two Frequency Synthesizers,” IEEE Transactions on Circuits and Systems -II, Vol. 54, No. 10, pp. 907–911, 2007. 

55. J. Lee, I. Nam, S.H. Cho and K. Lee, “Highly Linear and Low Noise 2.4-GHz RF Front-End Circuits Using Transformer and Vertical NPN BJT,” Electronics Letters, Vol. 43, No. 2, pp. 103–105, 2007. 

56. Y. Ku, I. Nam, S. Ha, K. Lee, and S.H. Cho, “Close-in Phase-Noise Enhanced Voltage-Controlled Oscillator Employing Parasitic V-NPN Transistor in CMOS Process,” IEEE Transactions on Microwave Theory and Techniques, Vol.54, No.4, pp.1363-1369, April 2006. 

57. B. Calhoun, D. Daly, N. Verma, D. Finchelstein, D. Wentzloff, A. Wang, S.H. Cho, and A.P. Chandrakasan, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes,” IEEE Transactions on Computers, Vol. 54, No. 6, 727 -740, 2005. 

58. S.H. Cho, A. Chandrakasan, “A 6.5GHz Energy-efficient BFSK modulator for wireless sensor applications”, IEEE Journal of Solid-State Circuits, Vol.39, No.5, pp.731-739, May 2004. 

59. E. Shih, S.H. Cho, F.S. Lee, B Calhoun, and A. Chandrakasan, “Design considerations for energy-efficient radios in wireless microsensor networks,” Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Vol.39, No.5, May 2004, pp.77-94. 

60. G. Manganaro, S.-U. Kwak, S.H. Cho, A. Pulincherry, “A Behavioral Modeling Approach to the Design of a Low Jitter Clock Source”, IEEE Transactions on Circuits and Systems -II: Analog and Digital Signal Processing, Vol. 50, No.11, pp.804-814, Nov. 2003. 

61. R. Min, M. Bhardwaj, S.H. Cho, N. Ickes, E. Shih, A. Sinha, A. Wang, A. Chandrakasan, “Energy-centric enabling technologies for wireless sensor networks” IEEE Wireless Communications, Vol. 9, No. 4, pp. 28–39, Aug. 2002. 

62. S.H. Cho, T. Xanthopoulos and A. Chandrakasan, “Design of Low Power Variable Length Decoder Using Fine Grain Non-Uniform Table Partitioning,” IEEE Transactions on VLSI Systems, vol.7, no.2, pp.249–257, June 1999.