Research

High-speed analog, mixed-signal and RF circuits

Memory interface

  • Quadrature signal corrector for DRAM interface

  • Supply noise immune clock distribution for low-power DRAM


Wireline Transceivers for Electrical Link

  • Low-power, high-bandwidth wireline transceiver for DRAM interface

  • Modulation, line-coding techniques (balanced-coded PAM-4, QAM) for noiseless and power-efficient design

  • High-speed circuit design for transceiver blocks (Transmitter, Receiver and Clock-path)

RF Frequency Synthesizer Design

  • Low in-band phase noise hybrid domain PLL

  • Low reference spur, low fractional spur digital PLL

  • Reference multiplied, cascaded PLL

  • Supply noise insensitive PLL

mm-Wave Frequency Synthesizer Design

  • W-band, V-band frequency synthesizer for radar application

  • Low frequency-error, low phase-noise PLL for FMCW frequency synthesizer

  • Fast chirp and wide frequency tuning range FMCW frequency synthesizer